A 1.5mW, 200MHz CMOS VCO for Wireless Biotelemetry

Few people have studied the problem of physiological data transmission at the rates required by NASA’s Life Sciences-Advanced BioTelemetry System (LSABTS). Implanted telemetry eliminates the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz RF transmitter suitable for short range biosensor and implantable use. A system architecture based on a frequency-locked loop frequency synthesizer is presented, and a novel differential frequency discriminator that eliminates the need for a frequency divider is also proposed. The Hajimiri phase noise model was used to optimize the VCO for minimum power consumption. A test chip was fabricated in a 0.5Pm, 3V CMOS process. Measured phase noise for a 1.5mW, 200MHz ring oscillator VCO is -80dBc/Hz at 100KHz offset, showing good agreement with the theory. Currently, NASA-Ames Research Center is developing the Life Sciences-Advanced BioTelemetry System (LS-ABTS) to conduct space-based animal research [1]. In vivo experiments require anesthetized animals and hard-wired connections to the implant creating a risk of infection due to transcutaneous wires. Wire breakage, movement artifacts, ground loops and 60Hz pick-up can also cause problems. In collaboration with the Fetal Treatment Center at UCSF, NASA is also developing a system for wireless telemetry of physiological parameters of fetuses for monitoring and identifying distress after pre-natal surgery [2]. An implant that will monitor heart rate, temperature, pH, and amniotic fluid pressure is required to operate in utero for up to 3 months. A low-power highly integrated radio transmitter is key to the success of these projects. The most important parameter of an implanted biotelemetry system is power dissipation. Power dissipation and implant lifetime determine the size of the battery which ultimately determines the size of the implant. A significant portion of the power budget for any implantable telemetry system is allocated to the generation of the RF carrier. Given this need for small, low-power wireless devices for biotelemetry, a low-power, integrated frequency synthesizer is required. Traditionally, frequency synthesizers have been implemented using a phase-locked loop (PLL). Figure 1 shows the block diagram and power budget for a state-of-the-art CMOS PLL synthesizer used in microprocessor clock generation [3]. In a PLL synthesizer, the VCO frequency is divided and then compared to a reference frequency by a phase detector. The phase detector drives a low-pass filter that generate the control voltage for the VCO. The major sources of power dissipation are the VCO (73%) and the frequency divider (22%). To reduce power we have to address these blocks first. We propose a frequency-locked loop (FLL) architecture (fig.2) that uses a differential frequency discriminator (DFD). In the past, quadricorrelators and rotational frequency detectors [4] have been used to aid the frequency acquisition process in a PLL, but have been superseded by simpler phase-frequency detectors with charge pumps [5]. The proposed FLL does not require a frequency divider, which represents 22% of the power budget for the PLL example just shown. The FLL can perform frequency comparison directly without a divider (N=1) by using a DFD implemented with switched capacitor circuits. In operation, current I1 is generated by switches S1, S2 and capacitor C1, and is inversely proportional to the reference frequency driving the switches, FREF, and the value of C1. Current I2 is also inversely proportional to the feedback frequency, and the value of C2. Current mirror M1/M2 force these two currents to be equal, resulting in the following relationship: FOUT = (C1/C2) FREF where the output frequency is determined solely by the capacitor ratio, C1/C2. A linear analysis using a single pole filter shows that this is a first order system, and thus inherently stable (neglecting sample-data effects). A PLL tracks the phase noise of the reference signal, relaxing the close-in phase noise requirements of the VCO (provided that the reference has better phase noise than the VCO). However, a FLL tracks the VCO’s frequency, not phase, forcing more stringent requirements on the VCO. The VCO’s power dissipation is determined by the frequency of operation and the phase noise performance required. In biotelemetry, data rates are low, and channel spacing wide, relaxing the phase noise requirements. This makes it feasible to use voltagecontrolled ring oscillators which are easy to integrate and do not require any external components. The VCO design is critical in the performance of the FLL synthesizer as the phase noise at the output of the FLL is solely a function of the phase noise of the VCO. The VCO consists of a 4-stage differential ring oscillator (fig.3). The differential buffers used (fig.4) have been shown to have excellent noise and power supply rejection characteristics [6]. Frequency control is achieved by changing the biasing of the buffer stages which determine the delay through each cell. The layout of the ring oscillator is symmetrical and load balanced to avoid any skewing between the phases. The Hajimiri phase noise model [7] was used to optimize the VCO for minimum power dissipation. The single-sideband phase noise of a differential